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Compact, High Efficiency, High Power Flash/Torch LED Driver with Dual Interface ADP1653
FEATURES
Small 6.4 mm x 7.2 mm solution 2.2 H power inductor 92% peak efficiency Tx masking within 50 s 2.1 A, 12 V power switch Pin-selectable interface: 2-bit logic or I2C(R) Programmable flash and torch current Up to 200 mA in torch mode Up to 500 mA in flash mode Programmable indicator LED current up to 20 mA Programmable timer register: up to 820 ms flash timeout 2.75 V to 5.5 V input voltage range Low noise, 1.2 MHz PWM operation Safety features Interrupt output pin Fault condition register Short-circuit protection Output overvoltage protection Thermal overload protection Integrated current limit and soft start Small 3 mm x 3 mm, 16-lead LFCSP footprint
GENERAL DESCRIPTION
The ADP1653 is a very compact, high efficiency, high power, camera-flash LED driver optimized for cellular phones. The device's high efficiency and dynamic LED current control improve flash brightness and picture quality in dimly lit environments. Efficiency peaks at 92% and is higher than charge pump solutions over the Li-Ion battery range. The device has a dual-mode interface that is configurable to 2-bit logic or an I2C interface. The indicator and high power LED currents are programmable with external resistors or through the I2C interface. To maximize overall flash brightness, the ADP1653 offers an input to reduce flash LED current in less than 50 s, referred to as the Tx mask. Tx masking reduces battery stress by scaling back flash LED current during an RF transmission. The ADP1653 solution requires only four external components in I2C mode and fits in a 6.4 mm x 7.2 mm space. The part integrates multiple safety features such as soft start, flash timeout, output current limit, thermal protection, and overvoltage protection. The ADP1653 operates over the -40C to +125C junction temperature range.
APPLICATIONS
Camera-enabled cellular phones, smart phones Digital still cameras, camcorders, PDAs
TYPICAL OPERATING CIRCUIT
INPUT VOLTAGE = 2.75V TO 5.5V 4.7F 2.2H ON OFF
16
PCB LAYOUT
LI-ION + INDUCTOR L1 C1 SCHOTTKY DIODE GND INPUT CAPACITOR
ON OFF 4.7F
15 14 13
UP TO 10.2V
STR
OPTIONAL TxMASK
1
EN
VDD
LX
PGND 12 INT 11 INTF 10
R5
D1
SETT SETF
2
ADP1653
ONE OR TWO LEDs
7.2mm C2 TO WHITE LEDs
3
CTRL1/SCL CTRL0/SDA
OUTPUT CAPACITOR PGND L = FDSE0312-2R2 CIN = GRM219R61A475K D1 = BAT20J COUT = GRM21BR61C475K FROM WHITE LEDs
06180-036
4
HPLED 9
ADP1653
R4
06180-001
SETI
5
ILED
6
OUT
7
GND
8
VDD
OPTIONAL (Tx MASK ONLY) 6.4mm
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 2.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
ADP1653 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Typical Operating Circuit................................................................ 1 PCB Layout........................................................................................ 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 I C Timing Specifications............................................................ 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Boundary Condition.................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7
2
Typical Performance Characteristics ..............................................9 Theory of Operation ...................................................................... 13 White LED Driver ...................................................................... 13 2-Bit Logic Interface Mode (INTF = 1)................................... 14 I2C Interface Mode (INTF = 0)................................................. 14 Turning on the Flash and Watchdog Timer ........................... 15 Safety Features ............................................................................ 16 Applications Information .............................................................. 17 Flash-Current Foldback During Transmit Pulse ................... 17 External Component Selection ................................................ 18 PCB Board Layout...................................................................... 19 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
1/07--Revision A: Initial Version
Rev. A | Page 2 of 24
ADP1653 SPECIFICATIONS
VDD = 3.0 V to 5.5 V, TJ = -40C to +125C, unless otherwise noted. 1 Table 1.
Parameter SUPPLY Input Voltage Range 2 Undervoltage Lockout Threshold Shutdown Current Soft Power-Down Current Conditions Min 3.0 2.80 2.58 Typ Max 5.5 2.95 2.75 1 45 45 700 700 3 3 0.5 0.5 Unit V V V A A A A A mA mA A A C
Operating Current 3
LX Leakage HPLED Leakage THERMAL SHUTDOWN Thermal Shutdown Threshold INPUTS EN, STR, CTRL1/SCL, CTRL0/SDA Input Logic Low Voltage Input Logic High Voltage SETI, SETT, SETF Input Logic High Voltage INTF Input Logic Low Voltage 4 Input Logic High Voltage4 INT OUTPUT Logic Low Output Voltage Logic High Leakage Current SETI, SETT, SETF REFERENCE VOLTAGE INDICATOR LED INTF = 1, SETI Current Source INTF = 0 WHITE LED DRIVER LX Switching Frequency Current Limit On Resistance OUT Soft Start Ramp Overvoltage Threshold Bias Current 5
VDD rising VDD falling EN = GND, TJ = -40C to +85C INTF = 0, EN = VDD, ILED register = 0, HPLED register = 0, TJ = -40C to +85C INTF = 1, EN = VDD, (CTRL1, CTRL0) = (0, 0), TJ = -40C to +85C INTF = 0, EN = VDD, ILED register = 001, HPLED register = 0 INTF = 1, (CTRL1, CTRL0) = (0, 1), RSETI = 200 k INTF = 0, EN = VDD, HPLED register = 00001 INTF = 1, (CTRL1, CTRL0) = (1, x) TJ = -40C to +85C TJ = -40C to +85C TJ rising
2.9 2.7 0.1 19 19 500 500 1.6 1.6 0.05 0.03 155
TJ = -40C to +85C TJ = -40C to +125C TJ = -40C to +85C TJ = -40C to +125C
0.54 0.48 1.26 1.27 1.4 VDD/2 - 0.6 VDD/2 + 0.6
V V V V V V V V A V mA mA mA mA
ISINK = -3 mA 1.19 RSETI = 25 k RSETI = 200 k ILED register = 1 (001 binary), SETI = VDD ILED register = 7 (111 binary), SETI = VDD 14.5 2.0 2.0 14.5 0.05 1.22 17.5 2.5 2.5 17.5
0.4 0.5 1.24 21.5 3.0 3.0 21.5
1.1 1.8
1.2 2.1 250 18 10.15
1.3 2.45 420
MHz A m V/ms V A
VDD rising VOUT = 10 V
9.8
10.5 12
Rev. A | Page 3 of 24
ADP1653
Parameter HPLED Regulation Voltage 6 Regulation Current INTF = 1, Torch Mode Flash Mode INTF = 0, Flash Mode Torch Mode Step Size for HPLED LSB Change Maximum Flash Timeout SETF RESPONSE (TRANSMIT MASKING FUNCTION)7 Conditions Boost active, two high power LEDs (HPLEDs) in series RSETT = 50 k or SETT = VDD RSETT = 125 k RSETF = 50 k RSETF = 500 k HPLED register = 11111 (binary), SETF = VDD HPLED register = 11000 (binary), SETF = VDD HPLED register = 00110 (binary), SETF = VDD HPLED register = 00001 (binary), SETF = VDD SETF = VDD INTF = 0 or 1, 983,040 x oscillator cycles HPLED current = 335 mA to 140 mA HPLED current = 140 mA to 335 mA
1 2 3
Min 0.23
Typ 0.32
Max 0.42
Unit V
110 35 460 35 460 365 110 38
125 50 500 50 500 395 125 50 15 820 22 24
145 60 550 60 550 435 145 60
mA mA mA mA mA mA mA mA mA ms s s
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25C, VDD = 3.6 V. This is the VDD input voltage range over which the rest of the specifications are valid. The part operates as expected until VDD goes below the UVLO threshold. This is the current into the VDD pin. Additional current can flow into the indicator LED or HPLED, depending on the mode selected. 4 INTF should be tied to GND (INTF = 0) for I2C interface or to VDD (INTF = 1) for hardwire interface. All other digital inputs are 1.8 V compatible. 5 This bias current is active only when the high power LED and/or indicator LED functions are enabled. 6 This specification is not valid during minimum on-time operation of the boost converter (one LED case) when excess voltage is dropped across the HPLED pin. 7 This specification is not production tested but is based on bench evaluation. It is based on the typical two-LED application circuit using a 100 k resistor from SETF to GND, and a 160 k resistor to a 1.8 V Tx mask logic signal with <1 s rise/fall time. HPLED register = 11001 (binary). The inductor current has settled to within 5% of final value.
Rev. A | Page 4 of 24
ADP1653
I2C TIMING SPECIFICATIONS
Table 2.
Parameter fSCL tHIGH tLOW tSU, DAT tHD, DAT1 tSU, STA tHD, STA tBUF tSU, STO tR tF tSP CB2
1
Min 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 + 0.1 CB 20 + 0.1 CB 0
Max 400
0.9
300 300 50 400
Unit kHz s s ns s s s s s ns ns ns pF
Description SCL clock frequency SCL high time SCL low time Data setup time Data hold time Setup time for repeated start Hold time for start/repeated start Bus free time between a stop and a start condition Setup time for stop condition Rise time of SCL and SDA Fall time of SCL and SDA Pulse width of suppressed spike Capacitive load for each bus line
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the SCL falling edge. 2 CB is the total capacitance of one bus line in picofarads.
SDA
tLOW
SCL
tR
tSU, DAT
tF
tF
tHD, STA
tSP
tR
tBUF
S
tHD, DAT
tHIGH
tSU, STA
Sr
tSU, STO
P
S
06180-002
S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION
Figure 3. I2C Interface Timing Diagram
Rev. A | Page 5 of 24
ADP1653 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VDD, CTRL0/SDA, CTRL1/SCL, INTF, EN, SETI, SETT, SETF, STR, HPLED to GND INT, ILED to GND LX, OUT to GND PGND to GND Operating Ambient Temperature Range Operating Junction Temperature Storage Temperature Range Soldering Conditions
1
THERMAL RESISTANCE
Rating -0.3 V to +6 V -0.3 V to + (VDD + 0.3 V) -0.3 V to +12 V -0.3 V to +0.3 V -40C to +125C1 125C -65C to +150C JEDEC J-STD-020
Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is dependent on the application and board layout. In applications where high maximum power dissipation exists, attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. For more information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). Table 4. Thermal Resistance
Package Type 16-Lead LFCSP Maximum Power Dissipation JA 44 1 Unit C/W W
In applications where high power dissipation and poor thermal resistance are present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(MAX)) is dependent on the maximum operating junction temperature (TJ(MAXOP) = 125C), the maximum power dissipation of the device (PD(MAX)), and the junction-to-ambient thermal resistance of the part/package in the application (JA), using the following equation: TA(MAX) = TJ(MAXOP) - (JA x PD(MAX)).
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
BOUNDARY CONDITION
Natural convection, 4-layer board, exposed pad soldered to the PCB.
ESD CAUTION
Rev. A | Page 6 of 24
ADP1653 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 STR
PIN 1 INDICATOR
15 EN
14 VDD 13 LX
SETT 1 SETF 2 CTRL1/SCL 3 CTRL0/SDA 4
12 PGND 11 INT 10 INTF 9 HPLED
TOP VIEW (Not to Scale)
ADP1653
ILED 6
GND 8
SETI 5
OUT 7
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 Mnemonic SETT Description Set Torch Input (2-Bit Logic Interface Only). SETT programs the high power LED current in torch mode. An external resistor connected between SETT and ground sets the torch current. When SETT is tied high, the current is internally set to 125 mA. In I2C mode, this pin is regarded as a no connect. Set Flash Input. SETF programs the high power LED (HPLED) current in flash mode and allows for transmit blanking of the LED. In 2-bit logic interface mode, an external resistor connected between SETF and ground sets the flash current. If SETF is tied high, the current is set internally to 500 mA. In I2C mode, the flash current scales with both the external resistor and the internal HPLED bits in the output select register. If SETF is tied high, an internal 50 k resistor combined with the HPLED bits set the HPLED current. Serial Interface Clock Input. In 2-bit logic interface mode, CTRL1 is the second input bit of the digital interface. In I2C mode, SCL is the clock input of the I2C-compatible serial interface. Serial Interface Data Input. In 2-bit logic interface mode, CTRL0 is the first input bit of the digital interface. In I2C mode, SDA is the data input/output of the I2C-compatible serial interface. Set Indicator Input (2-Bit Logic Interface Only). SETI programs the indicator LED current. An external resistor connected between SETI and ground sets the indicator LED (ILED) current. If SETI is tied high, the current is internally set to 10 mA. In I2C mode, this pin is regarded as a no connect. Indicator LED Input. Connect the cathode of the indicator LED to the ILED pin. Connect the anode to the battery or to a voltage rail greater than the LED forward voltage. White LED Output Voltage. OUT senses the output voltage of the white LED step-up converter. At startup, the ADP1653 limits the rate of increase of the voltage at OUT (soft start) to prevent excessive input inrush current. The OUT pin features a comparator to detect an overvoltage condition if the LED string is open circuited. Connect the anode of the white LED(s) to OUT. Connect a 3.3 F or greater capacitor between OUT and PGND. Analog/Digital Ground. Connect GND to PGND at the LFCSP paddle. High Power LED Current Regulator. HPLED regulates the current of the high power LED(s). Connect the cathode of the white LED string to HPLED. Interface Input. INTF selects the 2-pin interface mode. INTF is driven high to enable CTRL1 and CTRL0 for 2-bit logic interface mode. INTF is driven low to enable SDA and SCL for I2C interfacing. Active Low Interrupt Output. INT is an open-drain output that transitions from high to low to signal that a fault condition has occurred. INT should be connected via a pull-up resistor (for example, 10 k to 100 k) to the I/O supply rail and directly to the system processor. When an interrupt is detected, the system processor can read the FAULT register, using the I2C interface for details on the fault condition. Power Ground for Internal Switching FET. White LED Switch Node. LX drives the inductor of the white LED step-up converter. An inductor and diode connected to LX powers the white LEDs. Supply Input. Connect the battery between VDD and PGND. Bypass VDD to PGND with a 4.7 F or greater capacitor. Enable Input. Driving EN high turns on the ADP1653. Driving EN low disables the ADP1653 and reduces the input current to less than 1 A. When EN is high, disabling the LEDs puts the part into sleep mode, dropping the input current to less than 45 A. Strobe Control Input (I2C Interface Only). Driving STR high enables the flash function of the white LED. STR also enables the watchdog timer to prevent overstressing the white LEDs.
2
SETF
3 4 5
CTRL1/SCL CTRL0/SDA SETI
6 7
ILED OUT
8 9 10 11
GND HPLED INTF INT
12 13 14 15
PGND LX VDD EN
16
STR
Rev. A | Page 7 of 24
06180-003
ADP1653
Table 6. Mode Selection
Pin Mnemonic CTRL0/SDA CTRL1/SCL Value INTF = 0 (I2C Interface) SDA SCL INTF = 1 (2-Bit Logic Interface) CTRL1, CTRL0 = 0, 0 (ADP1653 disabled) CTRL1, CTRL0 = 0, 1 (ADP1653 indicator LED) CTRL1, CTRL0 = 1, 0 (ADP1653 torch mode) CTRL1, CTRL0 = 1, 1 (ADP1653 flash mode) ADP1653 disabled ADP1653 enabled Ignored Ignored Fault condition Normal operation SETI resistor sets indicator LED current 2 ILED current = 10 mA SETT resistor sets torch current2 Torch current = 125 mA SETF resistor(s) set flash current2 Flash current = 500 mA
EN STR INT SETI SETT SETF
Low High Low High Low High Resistor High Resistor High Resistor High
ADP1653 disabled ADP1653 enabled Flash disabled Flash enabled Fault condition Normal operation Ignored 1 I2C sets ILED current Ignored1 I2C sets torch current SETF resistor(s) and I2C set flash current and torch current 3 I2C sets flash current
If a resistor is present on SETI or SETT in I2C mode, it is ignored. Both pins should be tied high when operating in I2C mode. If a resistor is present, the current is set by this resistor. If a resistor is not present, the pin must be tied high and a default internal current set. 3 If a resistor is present on SETF in I2C mode, the output current scales with both the I2C setting and the external reference current. The SETF resistor scales both the flash mode and torch mode currents.
2
1
Rev. A | Page 8 of 24
ADP1653 TYPICAL PERFORMANCE CHARACTERISTICS
L = D2812C-2R0 : 138s
L = D2812C-2R0 : 132s
1
1
2
2
3 4
06180-011
3 4
CHANNEL 1 (I L) 0.5A/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV
CHANNEL 3 (V OUT) 5V/DIV CHANNEL 4 (STR) 5V/DIV
Figure 5. Startup, Two LEDs Flash Mode, LED Current = 335 mA, VDD = 3.2 V
L = D2812C-2R0 : 175s
Figure 8. Startup, Two LEDs Torch Mode, LED Current = 130 mA, VDD = 3.6 V
L = D2812C-2R0
1
1
2
2
3 4
06180-012
3 4
06180-015
06180-016
40s/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 3 (V OUT) 5V/DIV CHANNEL 4 (STR) 5V/DIV
400ns/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 3 (LX) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (HPLED NODE) 1V/DIV
Figure 6. Startup, Two LEDs Flash Mode, LED Current = 335 mA, VDD = 3.6 V
L = D2812C-2R0 : 153s
Figure 9. Inductor Current, Two LEDs Flash Mode, LED Current = 335 mA, VDD = 3.6 V
L = D2812C-2R0
1
1
2
2
3 4
3 4
06180-013
40s/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 3 (V OUT) 5V/DIV CHANNEL 4 (SCL) 5V/DIV
400ns/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 3 (LX) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (HPLED NODE) 1V/DIV
Figure 7. Startup, Two LEDs Torch Mode, LED Current = 130 mA, VDD = 3.2 V
Rev. A | Page 9 of 24
Figure 10. Inductor Current, Two LEDs Torch Mode, LED Current = 130 mA, VDD = 3.6 V
06180-014
40s/DIV
40s/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 3 (V OUT) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (SCL) 5V/DIV
ADP1653
: 22.4s
500 450 400 350
1
IHPLED (mA)
300 250 200 150 100 50
06180-037
2
3 4
06180-021 06180-023
0
0
5
10
15 HPLED CODE
20
25
30
40s/DIV CHANNEL 1 (IBAT) 0.5A/DIV CHANNEL 3 (V OUT) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (Tx MASK) 5V/DIV
Figure 11. HPLED Current vs. HPLED Code, I2C Mode, SETF = VDD
Figure 14. Tx Masking Response, Tx Mask 0 V to1.8 V, IHPLED = 335 mA to 140 mA, VDD = 3.2 V
: 23.2s
86 84 82
VDD = 4.2V
VDD = 3.6V
1
EFFICIENCY (%)
80
VDD = 3V VDD = 3.2V
2
78 76 74
3
72
150
200
250
300
350
400
LED CURRENT (mA)
06180-018
Figure 12. Efficiency PLED/PIN, Two High Power White LEDs in Series
Figure 15. Tx Masking Response, Tx Mask 0 V to1.8 V, IHPLED = 140 mA to 335 mA, VDD = 3.2 V
85
VDD = 3.2V VDD = 3.6V
1
80
EFFICIENCY (%)
75
2
70
VDD = 3V
65
L = LQM31P-2R2 DS = BAT20J D1 = PWF-3
VDD = 4.2V
3 4
0
100
200
300
400
500
HPLED CURRENT (mA)
06180-020
60
100ms/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 3 (INT) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (STR) 5V/DIV
Figure 13. Efficiency PLED/PIN, One High Power White LED
Figure 16. Flash Timed Mode, Two LEDs, Timer = 820 ms, IHPLED = 380 mA, VDD = 3.6 V
Rev. A | Page 10 of 24
06180-022
70 100
L = D2812C-2R0 DS = BAT20J D1, D2 = PWF-3
4
40s/DIV CHANNEL 1 (IBAT) 0.5A/DIV CHANNEL 3 (V OUT) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (Tx MASK) 5V/DIV
ADP1653
35 30 25
1
VDD = 5.5V VDD = 3.6V
IQ (A)
20 VDD = 3V 15 10 5 0 -50
2
3 4
06180-024
100ms/DIV CHANNEL 1 (I L) 0.5A/DIV CHANNEL 3 (INT) 5V/DIV CHANNEL 2 (I HPLED ) 0.2A/DIV CHANNEL 4 (STR) 5V/DIV
0
50 TEMPERATURE (C)
100
125
Figure 17. Flash Untimed Mode, Two LEDs, Timer = 300 ms, IHPLED = 380 mA, VDD = 3.6 V
2.5 HIGH 2.3
Figure 20. Quiescent Current vs. Temperature, EN = VDD, LED Functions Disabled
1.6 1.4 1.2 ILED ENABLED
LX CURRENT LIMIT (A)
IQ (mA)
2.1
MEDIUM
1.0 0.8 0.6
1.9 LOW
0.4
1.7
0.2
1.5 -40
0
10 60 TEMPERATURE (C) 110
06180-040
IQ = 21.5A
06180-028
0
1
2
3 VDD (V)
4
5
6
Figure 18. Typical Current Limit vs. Temperature; Low, Medium, and High Current Limit Parts
0.20 0.18 0.16
Figure 21. Quiescent Current vs. Temperature, VDD Swept from 5.5 V to 0 V, ILED Active at 2.5 mA Until UVLO Threshold
1.220 1.215 1.210
SHUTDOWN CURRENT (A)
FREQUENCY (MHz)
0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 -40
VDD = 3.6V
1.205 1.200 5.5V 1.195 1.190 1.185 1.180 1.175 3V 3.6V
VDD = 3V
VDD = 5.5V
10
60 TEMPERATURE (C)
110
125
06180-026
-15
10
35
60
85
110
TEMPERATURE (C)
Figure 19. Shutdown Current vs. Temperature, EN = 0 V
Figure 22. Oscillator Frequency vs. Temperature vs. VDD
Rev. A | Page 11 of 24
06180-029
1.170 -40
06180-027
ADP1653
127.5 127.0 126.5 126.0
3V 5.5V 352 353
351
IHPLED (mA)
125.0 124.5 124.0 123.5 123.0
IHPLED (mA)
125.5
3.6V
5.5V
350
3.6V 3V
349
348
06180-031
10
60 TEMPERATURE (C)
110
10
60 TEMPERATURE (C)
110
Figure 23. HPLED Regulation, Set at 125 mA, HPLED Register = 00110 (Binary), SETF = VDD
Figure 24. HPLED Regulation, Set at 350 mA, HPLED Register = 10101 (Binary), SETF = VDD
Rev. A | Page 12 of 24
06180-032
122.5 -40
347 -40
ADP1653 THEORY OF OPERATION
The ADP1653 is a high power, white LED driver ideal for driving white LEDs for use as a camera flash. The ADP1653 includes a step-up converter and a current regulator suitable for powering one, or up to three, high power, white LEDs. A second lower current sink allows an indicator LED to be driven with 2.5 mA to 17.5 mA current. The ADP1653 responds to a 2-pin control interface that can operate in two separate pin-selectable modes. Tying the INTF pin high enables a 2-bit logic hardwire interface. Tying the INTF pin low enables the I2C interface. When the required LED voltage is greater than the battery voltage, the NFET current regulator voltage at the HPLED pin is approximately 320 mV, and the step-up converter applies the appropriate voltage to OUT, allowing the LED to conduct the regulated current. When the white LED is turned on, the step-up converter output voltage slew is limited to 18 V/ms to prevent excessive battery current while charging the output capacitor. The output voltage of the step-up converter is sensed at OUT. If the output voltage exceeds the 10.15 V (typical) limit, the white LED converter turns off to indicate that a fault condition has occurred through the INT output and system registers. This feature prevents damage due to an overvoltage if the white LED string fails with an opencircuit condition. Setting the LED regulation currents depends on the 2-pin control interface used, as described in the following sections.
WHITE LED DRIVER
The ADP1653 drives a step-up converter to power typically one or two series-connected, high power LEDs. The white LED driver regulates the high power LED current for accurate brightness control. The ADP1653 uses an integrated NFET current regulator that drops the voltage when the power LED forward voltage is less than the battery voltage.
VDD = 2.75V TO 5.5V CIN L1 D1
7
PGND OUT
6
ILED
7
OUT
14
VDD
LX
13
COUT PGND
ILED CONTROL STR 16 EN 15 OVP
10.15V
2.7V
BIAS
OSCILLATOR UVLO
CTRL0/SDA 4 CTRL1/SCL 3
INTERFACE/ CONTROL
PWM CONTROLLER FAULT REGISTER
I/O VDD
THERMAL PROTECTION
11
- + VDD/2 0.32V
9
INT
HPLED
INTF
10
WATCHDOG TIMER
HIGH POWER LED CONTROL
x 400 = ILED
x 5200 = TORCH
x 20800 = FLASH
12
PGND
1.22V
IREF (ILED) 1.22V
5
1.22V
IREF 1.22V (TORCH) 1.22V
1
IREF (FLASH) 1.22V
2
8
GND
SETI
SETT
SETF
Tx MASK (OPTIONAL)
06180-004
RI
1.22V/RI
RT
1.22V/RT
RF
1.22V/RF
Figure 25. Detailed Block Diagram
Rev. A | Page 13 of 24
ADP1653
2-BIT LOGIC INTERFACE MODE (INTF = 1)
In 2-bit logic interface mode, the two control pins, CTRL1 and CTRL0, select whether the part is disabled or operating in indicator LED mode, torch mode, or flash mode, as outlined in Table 7. Table 7. 2-Bit Logic Interface Mode Selection
INTF = 1 Disabled ILED Torch Flash CTRL1 0 0 1 1 CTRL0 0 1 0 1 LED Current Setting Pin - SETI SETT SETF Default Current (SETx = H) - ILED = 10 mA HPLED = 125 mA HPLED = 500 mA
Consequently, the LED current resulting from an external resistor SETx is given by the following equation:
I LED = I DEFAULT x 50 k RSETx
(1)
where IDEFAULT is the LED current resulting from tying the SETx pin high. The values of IDEFAULT are given in Table 7 for indicator LED mode (SETI), torch mode (SETT), and flash mode (SETF) operation. For accurate LED current settings, the minimum SETx resistor values should be 25 k (SETI, SETT) or 50 k (SETF). The flash current can be quickly reduced with an external logic signal (typically 1.8 V logic) by adding a second external resistor from the SETF pin to the logic signal. Bringing this digital input from low to high toggles the flash from normal to reduced current mode by reducing the reference current supplied to the ADP1653 via the SETF pin (see the Applications Information section).
The LED current levels for indicator LED mode, torch mode, and flash mode operation are set with separate external resistors tied between ground and the SETI, SETT, and SETF pins, respectively. The resulting reference current into each SETx pin is equal to 1.22 V/RSETx. The reference current multiplied by a fixed ratio sets the relevant LED current. Table 8. Reference Current to LED Current Scaling
INTF = 1 Disabled ILED Torch Flash CTRL1 0 0 1 1 CTRL0 0 1 0 1 LED Current - IREF(SETI) x 400 IREF(SETT) x 5200 IREF(SETF) x 20,800
I2C INTERFACE MODE (INTF = 0)
The ADP1653 includes an I2C-compatible serial interface for control of LED current, as well as for readback of system status registers. The I2C chip address is 0x60 (0110 0000 (binary) in write mode). Figure 26 illustrates the I2C write sequence. The subaddress content selects which of the four ADP1653 registers is written to. Figure 27 shows the I2C read sequence. The ADP1653 sends the data from the register denoted by the subaddress. In this case, the fault register is read (REG3). The register definitions are shown in Figure 28. The lowest bit number (0) represents the least significant bit, and the highest bit number (7) represents the most significant bit.
Alternatively, a default internal current setting is used by tying the SETx pin high. The default current for each mode of operation approximately equals the current obtained with a 50 k resistor tied from the SETx pin to ground.
0 = WRITE ST 0 1 1 0 0 0 0 0 0 0 SUBADDRESS 0 SP ADP1653 RECEIVES DATA
ADP1653 ACK
CHIP ADDRESS
ADP1653 ACK
ADP1653 ACK
Figure 26. I2C Write Sequence
0 = WRITE ST 0 1 1 0 0 0 0 0 0
ADP1653 ACK
1 = READ 0 0 0 0 0 0 1 1 0
ADP1653 ACK
ST
0
1
1
0
0
0
0
1
0
ADP1653 ACK
06180-038
1 SP ADP1653 SENDS DATA
ADP1653 NO ACK
CHIP ADDRESS
SUBADDRESS
CHIP ADDRESS
Figure 27. I2C Read Sequence
Rev. A | Page 14 of 24
06180-039
ADP1653
OUT_SEL
OUTPUT SELECT D7 D6 D5 D4 D3 D2 D1 D0 REG0
HPLED<4:0> HIGH POWER LED CURRENT
ILED<2:0> INDICATOR LED CURRENT
CONFIG
TIMER CONFIGURATION
D7
D6
D5
D4
D3
D2
D1
D0
REG1
UNUSED TMR_CFG TIMER CONFIGURATION
TMR_SET<3:0> TIMER PERIOD SETTING
SW_STROBE
SOFTWARE STROBE
D7
D6
D5
D4
D3
D2
D1
D0
REG2
UNUSED SW_STROBE SOFTWARE STROBE ENABLE
FAULT
FAULT CONDITIONS
D7
D6
D5
D4
D3
D2
D1
D0
REG3
UNUSED FLT_SCP SHORT CIRCUIT FAULT FLT_OT OVER TEMPERATURE FAULT FLT_OV OVER VOLTAGE FAULT FLT_TMR TIMEOUT FAULT
Figure 28. I2C Register Assignments
The LED regulation current levels are controlled by writing to the ILED and HPLED registers. If the ILED register is set to 0, the ILED regulator is turned off and no current flows through the indicator LED. If the ILED register is programmed from 1 (001 binary) to 7 (111 binary), the indicator LED is continuously on, with a current scaled to the register setting given by IILED = 2.5 mA x Code where Code is the ILED register setting. Therefore, the ILED current can be programmed between 2.5 mA and 17.5 mA, using the full range of codes. If the HPLED register is set to 0, the HPLED regulator is turned off, and no current flows through the high power LED(s). If the HPLED register is programmed from 1 (00001 binary) to 11 (01011 binary), the regulator is in torch mode, and the HPLED remains continuously on, independent of the state of STR. If the HPLED register is programmed between 12 (01100 binary) and 31 (11111 binary), the HPLED regulator remains off until enabled through the strobe input (STR) or a software strobe command. To program a desired HPLED current with SETF tied high, use the following equation: IHPLED = 35 mA + Code x 15 mA where Code is the HPLED register setting. (3) (2)
Therefore, the HPLED torch current can be programmed between 50 mA and 200 mA for Code 1 to Code 11, and the HPLED flash current can be programmed between 215 mA and 500 mA for Code 12 to Code 31. Additionally, the HPLED current can be adjusted with an external resistor. This feature is primarily intended for limiting the LED flash current in handset applications when the phone's power amplifier transmits, but it can also be used to modify the HPLED current settings. If an external SETF resistor is present, the HPLED current is given by
06180-005
I HPLED = (35 mA + Code x 15 mA) x
50 k RSETF
(4)
TURNING ON THE FLASH AND WATCHDOG TIMER
A watchdog timer is always active in flash mode to prevent overstress of the HPLED. In 2-bit logic interface mode, users select flash operation by setting the CTRL1 pin and the CTRL0 pin high. The watchdog timer in this mode is fixed at 0.82 sec. Bringing the CTRLx pins to another state terminates the flash. If the state of the CTRLx pins remains high for longer than 0.82 sec, flash is automatically disabled by the watchdog timer, and the interrupt pin (INT) goes low to indicate a fault.
Rev. A | Page 15 of 24
ADP1653
In I2C mode, users select flash operation by programming the HPLED register between 12 (01100 binary) and 31 (11111 binary). The flash does not turn on until a strobe command is given by either pulling the STR pin high or by writing a software strobe command to the appropriate I2C register. There are additional settings for the watchdog timer in I2C mode. The strobe command operates in one of two watchdog timer modes, timed flash and user-controlled flash, that are controlled via the state of the timeout configuration (TMR_CFG) bit of the CONFIG register. If TMR_CFG is set (1), the flash operates in timed mode. In timed flash, a rising edge on STR turns on the flash. The flash remains on until the internal timeout occurs, which is set by the TMR_SET bits of the CONFIG register, according to the following equation: tFLASH = 820 ms - Code x 54.6 ms where Code ranges from 0 (0000 binary) to 15 (1111 binary), allowing for flash periods ranging from 54 ms to 820 ms. If TMR_CFG is not set (0), the flash operates in user-controlled timer mode. In user-controlled timer mode, the flash remains on as long as STR is held high. If STR remains high longer than TFLASH (if TMR_SET = 0, tFLASH = 820 ms), the flash is turned off and a fault is set in the watchdog timeout (FLT_TMR) bit of the FAULT register. The ADP1653 also offers a software strobe option, allowing the user to turn on the flash directly through the I2C interface without pulling the STR pin high. Setting the SW_STROBE register bit to 1 initiates a flash cycle. The strobe can operate in either timed or user-controlled mode, as previously described. (5)
Overvoltage Fault
The ADP1653 contains a comparator at the OUT pin that monitors the voltage from the high power LED(s) to PGND. If the voltage exceeds 10.15 V (typical), the ADP1653 shuts down (IQ < 45 A) and INT goes low. In I2C mode, Bit D0 in the FAULT register (FLT_OV) is read back as high. The ADP1653 is disabled, and INT remains low until the fault is cleared.
Timeout Fault
If the 2-bit logic interface is used, the maximum duration for flash being enabled (CTRL1/CTRL0 =1) is preset to 820 ms. If CTRL1 and CTRL0 remain high for longer than 820 ms, INT goes low and the ADP1653 is disabled. In I2C mode, if TMR_CFG is not set (0), and STR remains high for longer than tFLASH (see Equation 5), INT goes low and the FLT_TMR bit in the FAULT register is read back as high. The ADP1653 is disabled, and INT remains low until the fault is cleared.
Overtemperature Fault
If the junction temperature of the ADP1653 rises above 155C, a thermal protection circuit shuts down the LED driver and brings INT low. In I2C mode, Bit D2 (FLT_OT) of the FAULT register is read back as high. The ADP1653 is disabled, and INT remains low until the fault is cleared.
Short-Circuit Fault
The HPLED pin features short-circuit protection that disables the ADP1653 if it detects a short circuit to ground at the cathode of the LED(s). The ADP1653 monitors the HPLED voltage once the part is enabled in torch mode. If after 820 ms the HPLED pin remains grounded, a short circuit is detected. INT goes low, and Bit D3 (FLT_SCP) of the FAULT register is read back as high.
SAFETY FEATURES
Interrupts
For critical system conditions, such as output overvoltage, watchdog timeout, and overtemperature conditions, the ADP1653 indicates that an interrupt event has occurred by asserting the active-low interrupt output INT. INT is an open-drain output and should be pulled up to the I/O voltage rail by using a resistor. In I2C interface mode, the system baseband processor can read the fault register through the I2C interface to determine the nature of the fault condition after sensing that INT has gone low. Users can clear a fault by writing 0x00 to the OUT_SEL register. This brings INT high and clears the FAULT register. In 2-bit logic interface mode, INT goes low for the same fault conditions, but I2C register readback is not available. To clear a fault, set CTRL1 and CTRL0 low.
Input Undervoltage
The ADP1653 includes an input undervoltage lockout circuit. If the battery voltage drops below the 2.7 V (typical) input UVLO threshold, the ADP1653 shuts down and the input current drops to less than 45 A to prevent deep discharge of the battery. In this case, the system register information is lost, and when power is reapplied, a power-on reset circuit resets the registers to their default conditions.
Current Limit
The internal LX switch limits battery current by ensuring that the peak inductor current does not exceed 2.1 A (typical). If the SETI, SETT, or SETF pins accidentally connect to ground, reference current is limited to a maximum of 1 mA.
Rev. A | Page 16 of 24
ADP1653 APPLICATIONS INFORMATION
FLASH-CURRENT FOLDBACK DURING TRANSMIT PULSE
The ADP1653 allows a fast, 1.8 V logic-enabled foldback of the flash current, typically enabled shortly before an RF transmit pulse. This feature extends the life of the battery by preventing overstress of the battery cell. It also extends the life of the phone by reducing the maximum instantaneous system current that can occur, allowing a lower battery operating voltage limit. A logic high to R2 changes the direction of the current in R2. IREF = IR1 - IR2 (7)
I REF =
1.22 V VTx mask - 1.22 V - R1 R2
(8) (9)
IHPLED = IREF x 20,800 The ratio of full flash current to reduced flash current for a 1.8 V logic signal is approximately
Full Flash Reduced Flash = R2 + R1 R1 R2 - 2
2-Bit Logic Interface Mode (INTF = 1)
In 2-bit logic interface mode, the flash current is set with an external resistor. The 1.22 V reference voltage is buffered to the SETF pin, generating a reference current across an external SETF resistor. This reference current is multiplied by a fixed gain to set the flash current in the HPLED. A 1.8 V compatible logic signal selects normal or reduced flash current by adjusting the reference current, as shown in Figure 29 and Figure 30.
CURRENT MIRRORS IREF 1.22V
(10)
If R1 = R2 = 100 k, maximum flash current is 500 mA, and reduced flash current is 125 mA.
I2C Mode (INTF = 0)
To allow flash current foldback in I2C mode, the user should connect a resistor between SETF and ground, and another resistor from SETF to the logic input, as shown in Figure 29 and Figure 30. Operation is the same as for the 2-bit logic interface mode, except the flash current is additionally scaled by setting the HPLED bits in the OUT_SEL register. Full-current flash mode (Tx mask = 0 V) has a flash current of
I HPLED = (35 mA + Code x 15 mA) x 50 k RSETF
(11)
1.22V R2 DIGITAL OUTPUT TxMASK = 0V 1.22V/R2 R1 SETF 1.22V/R1
where:
06180-006
RSETF is a parallel combination of R1 and R2. Code is the HPLED register setting. Bring the Tx mask voltage high for reduced reference current. Therefore, the reduced LED current is IHPLED (see Equation 13). I REF =
(6)
Figure 29. Flash Mode Current Foldback (Normal Operation with R2 Grounded Through Digital Control Signal)
Full-current flash mode has a reference current of
1.22 V R1
I REF _ 0
1.22 V 1.22 V x (R1 + R2) = = R1// R2 R1 x R2
-
VTx mask - 1.22 V R2
(12)
The reference current is multiplied by a fixed gain to give the actual flash current (see Table 8).
CURRENT MIRRORS IREF 1.22V
I HPLED = (35 mA + Code x 15 mA) x
50 k x I REF 1.22 V
(13)
1.22V R2 0.6V/R2 R1 SETF
06180-007
1.8V DIGITAL OUTPUT TxMASK = 1.8V
1.22V/R1
Figure 30. Flash Mode Current Foldback with 1.8 V Signal Applied to R2
Rev. A | Page 17 of 24
ADP1653
EXTERNAL COMPONENT SELECTION
Selecting the Inductor
The ADP1653 step-up converter increases the battery voltage to allow driving one, two, or three LEDs, whose combined voltage drop is higher than the battery voltage plus the 0.32 V (typical) current source headroom voltage. This allows the converter to regulate the HPLED current over the entire battery voltage range and with a wide variation of LED forward voltage. Users should choose an inductor value such that the inductor ripple current is approximately 2/5th of the maximum dc input load current. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. For most applications, an inductor in the range of 1.5 H to 3.3 H works well. To determine the inductor ripple current, users should first calculate the switch duty cycle for the step-up converter, which is determined by the input voltage (VIN), output voltage (VOUT), and Schottky forward voltage (VF). VOUT equals the LED voltage drop plus 320 mV (typical) overhead for the HPLED current regulator.
VIN = 1- D VOUT + VF
The inductor saturation current should be greater than the sum of the dc input current and half the inductor ripple current. A reduction in the effective inductance due to saturation increases the inductor current ripple but improves loop stability, reducing the amount of output capacitance required. Ensure that the peak inductor current (dc + 1/2 of inductor ripple) is less than the LX minimum current limit (1.5 A).
Selecting the Input Capacitor
The ADP1653 requires an input bypass capacitor to supply transient currents while maintaining constant input and output voltage. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. Use an input capacitor with sufficient ripple current rating to handle the inductor ripple. A 4.7 F X5R/X7R ceramic capacitor rated for 6.3 V is the minimum recommended input capacitor. Increased input capacitance reduces the amplitude of the switching frequency ripple on the battery. Because of the dc bias characteristics of ceramic capacitors, a 0603, 6.3 V X5R/X7R, 10 F ceramic capacitor is preferable.
Selecting the Diode
The ADP1653 is a nonsynchronous boost and, as such, requires an external Schottky rectifier to conduct the inductor current to the output capacitor and HPLEDs when the LX switch is off. Ensure that the Schottky peak current rating is greater than the maximum inductor current. Choose a diode with an average current rating that is significantly larger than the maximum LED current. To prevent thermal runaway, derate the Schottky rectifier to ensure reliable operation at high junction temperatures. To achieve the best efficiency, select a Schottky diode with a low VF.
(14)
Solving for D
D = 1- V + VF - VIN VIN = OUT VOUT + VF VOUT + VF
The HPLED (output) current is regulated as low as 50 mA (torch mode) and as high as 500 mA (flash mode). The maximum dc input current is related to the maximum dc output current by the following equation:
Selecting the Output Capacitor
(15) The output capacitor maintains the output voltage and supplies the HPLED current when the LX switch is on. It also stabilizes the loop. A 4.7 F, 16 V X5R/X7R ceramic capacitor is generally recommended. The minimum required capacitance for loop stability for the two-LED and one-LED cases is shown in Figure 31 and Figure 32, respectively. Choose a capacitor with a capacitance greater than the minimum shown in Figure 31 and Figure 32 for the worst case dc bias voltage and temperature condition. Note that dc bias characterization data is available from capacitor manufacturers and should be taken into account when selecting input and output capacitors.
I IN ( MAX )
V = IOUT ( MAX ) x OUT V IN
1 x
where is efficiency (assume 0.80 in the two-LED case). Choose the initial inductor value by using the equation
L=
where:
VIN I L x f SW
VOUT + VF - VIN V OUT + VF

(16)
L is the inductor value (reduce L to reduce solution size). fSW is the switching frequency. IL is the inductor ripple current, typically 2/5th of the maximum dc input current. VF is the forward voltage of the Schottky diode.
Rev. A | Page 18 of 24
ADP1653
4.5 4.0 MINIMUM CAPACITANCE (F) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 OUT OUT OUT OUT 0 100 200 300 = 6.3V, = 6.3V, = 8.3V, = 8.3V, VDD VDD VDD VDD = 3.2V = 4.2V = 3.2V = 4.2V 500
06180-033
OUT = 6.3V, OUT = 6.3V, OUT = 8.3V, OUT = 8.3V,
VDD VDD VDD VDD
= 3.2V = 4.2V = 3.2V = 4.2V
PCB BOARD LAYOUT
3.3H + 20%
Good PCB layout is important to maximize efficiency and to minimize noise and electromagnetic interference (EMI). An example PCB layout is shown in Figure 34. Refer to the following guidelines for adjustment to the suggested layout. The high current paths are shown in Figure 35. Place components that are on high current paths first. To minimize large current loops, place the input capacitor, inductor, Schottky diode, and output capacitor as close as possible to each other and to the ADP1653 using wide tracks (use shapes where possible). Use separate analog and power ground planes. The analog ground plane is used to ground the SETI, SETT, and SETF resistors and for any digital connections (that is, INTF = 0 = AGND). Use the power ground plane to ground the power components. Connect the input capacitor, output capacitor, and the PGND pin (Pin 12) to the PGND plane. If it is not possible to make the PGND plane continuous, use a number of low inductance vias to connect the planes. Connect the AGND and PGND planes at the paddle or close to the paddle of the ADP1653. The SETI, SETT, and SETF resistors set a small reference current that generates the LED current. To minimize noise and current error, connect the SETI, SETT, and SETF resistors as close as possible to the ADP1653. Connect the other end of the resistors directly to the AGND plane. Connect the output capacitor to the high power LED(s), using a wide, low resistance trace. Connect the bottom of the LED string back to the HPLED pin (Pin 9) with a wide trace. The GND pin (Pin 8) is connected to the source of the current regulator NFET. Ensure that there is a low impedance back to the battery for the high power LED current by connecting the GND pin to the PGND plane with a low impedance via(s) close to the GND pin. The OUT pin is used for soft start and contains a comparator for overvoltage protection. Connect the output capacitor back to the OUT pin (Pin 7) with a direct trace. The trace does not need to be wide.
2.2H + 20%
400
HPLED CURRENT, 2 LED CASE (mA)
Figure 31. Minimum Output Capacitance for L = 3.3 H + 20% and L = 2.2 H + 20% for Two-LED Designs
4.0 3.5
MINIMUM CAPACITANCE (F)
OUT = 3.3V, VDD = 3.2V
3.0 OUT = 4.3V, VDD = 4.2V 2.5 2.0 1.5 1.0 0.5 0 2.2H + 20%
OUT = 4.3V, VDD = 3.2V
0
50
100
150
200
250
300
350
400
450
500
HPLED CURRENT, 1 LED CASE (mA)
Figure 32. Minimum Output Capacitance for L = 2.2 H + 20% for One-LED Design
5.0 4.5 4.0 -40C (10V)
CAPACITANCE (F)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 DC BIAS (V) 8 10 12
06180-008
+85C (10V)
0
Figure 33. DC Bias Characteristic of a 10 V, 4.7 F Ceramic Capacitor
06180-030
Rev. A | Page 19 of 24
ADP1653
VIN INPUT CAPACITOR INDUCTOR GND PGND PLANE
C1
SCHOTTKY DIODE AGND PLANE L1 D1
HIGH-POWER LED
D3 OUTPUT CAPACITOR
C2 SETT RESISTOR R6 INDICATOR LED
SETF RESISTOR R5
PGND
D4
R4
HIGH-POWER LED
TxMASK RESISTOR SETI RESISTOR R7
ADP1653
D2
PGND CONNECT AGND TO PGND CLOSE TO IC. THIS IS THE GND RETURN PATH FOR HPLED CURRENT, SO A REASONABLY LARGE VIA SHOULD BE USED TO CONNECT AGND TO PGND PLANE.
Figure 34. Example Layout of ADP1653 Driving Two White LEDs, Pink = GND Layer, Gray/Green = Top Layer (a One-LED Layout Is Similar)
INPUT VOLTAGE = 2.75V TO 5.5V 4.7F 2.2H
4.7F
16 15 14 13
STR
EN
VDD
LX
OPTIONAL Tx MASK
1
SETT SETF
PGND 12 INT 11 INTF 10 HPLED 9
OUT
7
2
ADP1653
ONE OR TWO LEDs
3
CTRL1/SCL CTRL0/SDA
SETI ILED
5 6
4
GND
8
06180-035
VDD
Figure 35. Typical Applications Circuit (High Current Lines Are Shown in Bold)
Rev. A | Page 20 of 24
06180-034
ADP1653 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 0.90 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 1.50 REF 0.60 MAX 0.50 0.40 0.30
PIN 1 INDICATOR
*1.65 1.50 SQ 1.35
13 12
16
EXPOSED PAD
1
9 (BOTTOM VIEW) 4 8 5
0.25 MIN
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP1653ACPZ-R2 1 ADP1653ACPZ-R71 ADP1653-EVALZ1
1
Temperature Range -40C to +125C -40C to +125C
Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-16-3 CP-16-3
Branding L3H L3H
Z = Pb-free part.
Rev. A | Page 21 of 24
ADP1653 NOTES
Rev. A | Page 22 of 24
ADP1653 NOTES
Rev. A | Page 23 of 24
ADP1653 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06180-0-1/07(A)
Rev. A | Page 24 of 24

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